A) Field of the Invention
This invention relates to a solid state imaging apparatus, especially relates to a structure of the solid state imaging apparatus for a digital still camera.
B) Description of the Related Art
FIG. 9 is a schematic plan view of a conventional solid state imaging apparatus 100.
The solid state imaging apparatus 100 includes a light receiving region 2 including a multiplicity of photoelectric conversion elements 12 and vertical electric charge transfer devices (VCCD) 14 that vertically transfer signal electric charges generated by the multiplicity of photoelectric conversion elements 12, a line memory 5 that temporally accumulates the signal electric charges transferred by the VCCD 14, a horizontal electric charge transfer device (HCCD) 3 that receives the signal charges from the line memory 5 to horizontally transfer and an output amplifier (output circuit) 4 that converts the signal electric charges to voltage to output.
In the light receiving region 2 of an imaging apparatus adopting a pixel interleaved array CCD (PIACCD) shown in the drawing, the multiplicity of the photoelectric conversion elements 12 are arranged in the so-called pixel interleaved arrangement. In each space between columns of the photoelectric conversion elements 12, a vertical electric charge transfer device 14 that reads out and vertically transfers the signal electric charges generated in the photoelectric conversion elements 12 are positioned vertically with weaving through the space of the photoelectric conversion elements 12. Each transfer channel is arranged in the weaving space formed by the pixel interleaved arrangement, and the adjacent transfer channels apart from each other via the photoelectric conversion element and come closer to each other via a channel stop region (not shown in the drawing). For example, the details of the pixel interleaved arrangement can be found in Japanese Laid-Open Patent Hei10-136391 and Tetsuo Yamada, et al, February, 2000, “A Progressive Scan CCD Imager for DSC Applications”, ISSCC Digest of Technical Papers, Page 110 to 111.
Each vertical electric charge transfer device 14 is consisted of a vertical transfer channel (not shown in the drawing) and transfer electrodes formed to horizontally weave through a space between the photoelectric conversion elements 12 on an insulating film (not shown in the drawing) over the vertical transfer channel.
In the prior art shown in the drawing, it is shown an example wherein all the pixels 12 perform photoelectric conversion of image information in same color (P1 to P4). The same color is, for example, one of three primary colors of red (R), blue (B) and green (G) or white, etc. Moreover, the symbols P1 to P4 are added to every line (every line or row of the photoelectric conversion element) for convenience of an explanation; however, all of the photoelectric conversion elements 12 have same function for picking up the same colored image signals.
Normally, the signal charges photoelectric-converted by the pixels 12 of the P1 and the P2 are transferred by the same transfer line of the VCCD 14 in parallel. The P3 and the P4 are also transferred by the same transfer line in parallel. The last transfer line of the VCCD 14 is continued with the CCD line memory (LM) 5, and the transferred signal electric charges are accumulated in the line memory 5.
A technique for adding the same colored adjacent signals is used for improving a frame rate (the number of frames/sec.) at a time of animation photographing or for taking a dark scene brightly.
In the drawing, the line memory 5 and the multi-phase HCCD 3 have a function for mixing the same colored horizontally adjacent signal electric charges by addition. Only the P1 signals are transferred to the HCCD 3 by imposing high-level voltage only to the φ2A and the φ2B to make the LM a low level. Then, the P1 signals move under the electrodes of φ1A and the φ1B by imposing a low-level voltage on the electrodes of the φ2A and the φ2B and imposing a high-level voltage on the φ1A and φ1B, and the P2 signals are transferred from the line memory 5. Then, the P1 signals and the P2 signals are added in the HCCD 3.
As described in the above, an amount of the electric charges for one signal is amplified in twice, and the number of the pixels of the image output becomes a half. The necessary time for outputting the signals of all the pixels can be decreased to a half. As a result, sensitivity and the frame rate can be doubled comparing to those in the conventional technique.
Recently as a number of pixels in a solid state imaging device increases, a four-pixel addition technique becomes effective to further improvement of sensitivity. In this case, horizontal resolution will be one quarter and a gap in a horizontal direction greatly increases when horizontally adjoining four pixels are added. Therefore, in the four-pixel addition technique, it is preferable to add horizontally adjoining two pixels and vertically adjoining two pixels.
FIG. 10 are schematic views for explaining the 4-pixel addition (mixture by addition) by the conventional solid state imaging apparatus 100.
FIG. 10A shows an arrangement when the signals have been transferred from the pixels 12 to the VCCD 14. The first line to which the P2 signals and the P1 signals are alternatively arranged and the second line to which the P4 signals and the P3 signals are alternatively arranged are arranged alternatively.
FIG. 10B shows a transition of a condition from a condition wherein the P2 and P1 signals of the first line have been transferred to the line memory 5, and then the P4 and P3 signals of the second line are transferred to the line memory 5 so as to the signals of the two lines are added together in the line memory 5 to a condition wherein only signal columns where the P1 and P3 signals have been added are selectively transferred to the HCCD 3 and, in addition to that, the signals transferred to the HCCD 3 are shifted by one step to a left direction (a direction toward the output) inside the HCCD 3. Thereafter, as shown in FIG. 10C, signal columns where the P2 and P4 signals have been added are transferred to the HCCD 3, and the signal electric charges of P1 to P4 are added in the HCCD 3. By repeating the above-described series of operations, time sequential outputs of four-pixel addition as shown in FIG. 10D can be obtained from the signal arrangement shown in FIG. 10A.
FIG. 11A is a schematic plan view of the light receiving region 2 showing a combination of four pixels added by the four-pixel addition by the conventional solid state imaging apparatus 100. A sampling unit of an image will be a region enclosed by a parallelogram as shown in the drawing. FIG. 11B and FIG. 11C show two-dimensional Nyquist limits wherein a center of the sampling unit (shown by a black circle) is placed as a center of an image sampling (the image sampling center).
FIG. 11B is a graph representing the Nyquist limits without the addition, and FIG. 11C is a graph representing the Nyquist limits with the conventional four-pixel addition shown in FIG. 10.
Since each pixel forms a tetragonal matrix with an arrangement pitch 2 in a horizontal and a vertical directions with other pixels, the two-dimensional Nyquist limits in case of outputting the signals of all the pixels independently without pixel addition will be 1 p in the horizontal and the vertical directions, that is, the Nyquist limits in both horizontal and vertical directions become the same.
When the conventional four-pixel addition shown in FIG. 10 is executed, the Nyquist limit in the horizontal direction will be a half of that without the pixel addition, and the Nyquist limit in the vertical direction will be a quarter of that without the pixel addition. That is, vertical resolution will be a half of horizontal resolution. Moreover, since the shape of the sampling unit is asymmetry in the horizontal and vertical directions, a MTF property (resolution property) will be changed significantly according to a direction.